AT91SAM9G20B-CFU【PDF 16/42 页】IC MCU ARM9 247-LFBGA

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6384DS–ATARM–13-Jan-10

AT91SAM9G20 Summary

Programming facilities

– Word, half-word, byte access

– Automatic page break when Memory Boundary has been reached

– Multibank Ping-pong Access

– Timing parameters specified by software

– Automatic refresh operation, refresh rate is programmable

Energy-saving capabilities

– Self-refresh, power down and deep power down modes supported

Error detection

– Refresh Error Interrupt

SDRAM Power-up Initialization by software

CAS Latency of 1, 2 and 3 supported

Auto Precharge Command not used

8.2.4

Error Corrected Code Controller

Hardware Error Corrected Code (ECC) Generation

– Detection and Correction by Software

Supports NAND Flash and SmartMedia Devices with 8- or 16-bit Data Path.

Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes,

Specified by Software

Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data

Path

Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes

with 8-bit Data Path

Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes

with 8-bit Data Path

System Controller

The System Controller is a set of peripherals, which allow handling of key elements of the sys-

tem, such as power, resets, clocks, time, interrupts, watchdog, etc.

The System Controller User Interface embeds also the registers allowing to configure the Matrix

and a set of registers for the chip configuration. The chip configuration registers allows

configuring:

– EBI chip select assignment and Voltage range for external memories

The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address

space, between addresses 0xFFFF E800 and 0xFFFF FFFF.

However, all the registers of System Controller are mapped on the top of the address space. All

the registers of the System Controller can be addressed from a single pointer by using the stan-

dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes.

Figure 9-1 on page 24 shows the System Controller block diagram.

Figure 8-1 on page 19 shows the mapping of the User Interfaces of the System Controller

peripherals.

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